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  <title>Config</title>
  <meta name="author" content="Daniel Reimer">
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 content="Lists the Settings in the Config Script in RosBE.">
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<dl>
  <dt><span style="font-weight: bold; font-style: italic;">SARCH:</span><br>
    <span style="font-weight: bold; text-decoration: underline;"></span></dt>
  <dt>Sub-architecture to build for. Right now you can only select
xbox, which enables some code needed to run ROS on a XBox 1</dt>
</dl>
<span style="font-weight: bold; font-style: italic;">OARCH:</span><br>
Generate instructions for this CPU type. See CPU Type list below.
<dl>
  <dt><span style="font-weight: bold; font-style: italic;">TUNE:</span><br>
  </dt>
  <dt>Which CPU ReactOS should be optimized for.&nbsp; Specify one of
the above CPUs or generic. When this option is not used, GCC will
optimize for the processor specified by OARCH.See CPU Type list below.</dt>
</dl>
<span style="font-weight: bold; font-style: italic;">OPTIMIZE:</span><br>
What level of optimisation to use.
<dl>
  <dt><span style="font-weight: bold; font-style: italic;">KDBG:</span><br>
  </dt>
  <dt>Whether to compile in the integrated kernel debugger.</dt>
</dl>
<span style="font-weight: bold; font-style: italic;">DBG:</span><br>
Whether to compile for debugging. No compiler optimizations will be
performed.
<dl>
  <dt><span style="font-weight: bold; font-style: italic;">GDB:</span><br>
  </dt>
  <dt>Whether to compile for debugging with GDB. If you don't use GDB,
don't enable this.</dt>
</dl>
<span style="font-weight: bold; font-style: italic;">NSWPAT</span><span
 style="font-weight: bold; font-style: italic;">:</span><br>
Whether to compile apps/libs with features covered software patents or
not. If you live in a country where software patents are valid/apply,
don't enable this (except they/you purchased a license from the patent
owner).
<dl>
  <dt><span style="font-weight: bold; font-style: italic;">_WINKD_</span><span
 style="font-weight: bold; font-style: italic;">:</span><br>
  </dt>
  <dt>Whether to compile with the KD protocol. This will disable
support for KDBG as well as rossym and symbol lookups, and allow WinDBG
to connect to ReactOS. This is currently not fully working, and
requires kdcom from Windows 2003 or TinyKRNL. Booting into debug mode
with this flag enabled will result in a failure to enter GUI mode. Do
not enable unless you know what you're doing.</dt>
</dl>
<span style="font-weight: bold; font-style: italic;">_ELF_</span><span
 style="font-weight: bold; font-style: italic;">:</span><br>
Whether to compile support for ELF files. Do not enable unless you know
what you're doing.
<dl>
  <dt><span style="font-weight: bold; font-style: italic;">BUILD_MP</span><span
 style="font-style: italic;">:</span><br>
  </dt>
  <dt>Whether to compile the multi processor versions for ntoskrnl and
hal.</dt>
  <br>
  <br>
</dl>
<span style="text-decoration: underline; font-style: italic;">CPU Type
List:</span><br>
<br>
<table style="text-align: left; width: 100%;" border="1" cellpadding="2"
 cellspacing="2">
  <tbody>
    <tr>
      <td style="vertical-align: top;"><em>i386</em></td>
      <td style="vertical-align: top;">Intel's i386 CPU. (No scheduling
is implemented for this chip.) </td>
    </tr>
    <tr>
      <td style="vertical-align: top;"><em>i486</em></td>
      <td style="vertical-align: top;">Intel's i486 CPU. (No scheduling
is implemented for this chip.) </td>
    </tr>
    <tr>
      <td style="vertical-align: top;"><em>i586, pentium</em></td>
      <td style="vertical-align: top;">Intel Pentium CPU with no MMX
support. </td>
    </tr>
    <tr>
      <td style="vertical-align: top;"><em>pentium-mmx</em></td>
      <td style="vertical-align: top;">Intel PentiumMMX CPU based on
Pentium core with MMX instruction set support. </td>
    </tr>
    <tr>
      <td style="vertical-align: top;"><em>i686, pentiumpro</em></td>
      <td style="vertical-align: top;">Intel PentiumPro CPU. </td>
    </tr>
    <tr>
      <td style="vertical-align: top;"><em>pentium2</em></td>
      <td style="vertical-align: top;">Intel Pentium2 CPU based on
PentiumPro core with MMX instruction set support. </td>
    </tr>
    <tr>
      <td style="vertical-align: top;"><em>pentium3, pentium3m</em></td>
      <td style="vertical-align: top;">Intel Pentium3 CPU based on
PentiumPro core with MMX and SSE instruction set
support. </td>
    </tr>
    <tr>
      <td style="vertical-align: top;"><em>pentium-m</em></td>
      <td style="vertical-align: top;">Low power version of Intel
Pentium3 CPU with MMX, SSE and SSE2 instruction set
support. Used by Centrino notebooks. </td>
    </tr>
    <tr>
      <td style="vertical-align: top;"><em>pentium4, pentium4m</em></td>
      <td style="vertical-align: top;">Intel Pentium4 CPU with MMX, SSE
and SSE2 instruction set support. </td>
    </tr>
    <tr>
      <td style="vertical-align: top;"><em>prescott</em></td>
      <td style="vertical-align: top;">Improved version of Intel
Pentium4 CPU with MMX, SSE, SSE2 and SSE3 instruction
set support. </td>
    </tr>
    <tr>
      <td style="vertical-align: top;"><em>nocona</em></td>
      <td style="vertical-align: top;">Improved version of Intel
Pentium4 CPU with 64-bit extensions, MMX, SSE,
SSE2 and SSE3 instruction set support. </td>
    </tr>
    <tr>
      <td style="vertical-align: top;"><span style="font-style: italic;">core2</span><br>
      </td>
      <td style="vertical-align: top;">Intel Dual Core CPU, MMX, SSE,
SSE2 and SSE3 instruction set support.<br>
      </td>
    </tr>
    <tr>
      <td style="vertical-align: top;"><em>k6</em></td>
      <td style="vertical-align: top;">AMD K6 CPU with MMX instruction
set support. </td>
    </tr>
    <tr>
      <td style="vertical-align: top;"><em>k6-2, k6-3</em></td>
      <td style="vertical-align: top;">Improved versions of AMD K6 CPU
with MMX and 3dNOW! instruction set support. </td>
    </tr>
    <tr>
      <td style="vertical-align: top;"><em>athlon, athlon-tbird</em></td>
      <td style="vertical-align: top;">AMD Athlon CPU with MMX, 3dNOW!,
enhanced 3dNOW! and SSE prefetch instructions
support. </td>
    </tr>
    <tr>
      <td style="vertical-align: top;"><em>athlon-4, athlon-xp,
athlon-mp</em></td>
      <td style="vertical-align: top;">Improved AMD Athlon CPU with
MMX, 3dNOW!, enhanced 3dNOW! and full SSE
instruction set support. </td>
    </tr>
    <tr>
      <td style="vertical-align: top;"><em>k8, opteron, athlon64,
athlon-fx</em></td>
      <td style="vertical-align: top;">AMD K8 core based CPUs with
x86-64 instruction set support. (This supersets
MMX, SSE, SSE2, 3dNOW!, enhanced 3dNOW! and 64-bit instruction set
extensions.) </td>
    </tr>
    <tr>
      <td style="vertical-align: top;"><span style="font-style: italic;">opteron-sse3</span><br>
      </td>
      <td style="vertical-align: top;">AMD K8 core based CPUs with
x86-64 instruction set support. (This supersets
MMX, SSE, SSE2, SSE3, 3dNOW!, enhanced 3dNOW! and 64-bit instruction
set
extensions.)</td>
    </tr>
    <tr>
      <td style="vertical-align: top;"><span style="font-style: italic;">barcelona</span><br>
      </td>
      <td style="vertical-align: top;">AMD Multi Core CPU. MMX, SSE,
SSE2, SSE3, 3dNOW!, enhanced 3dNOW! Support</td>
    </tr>
    <tr>
      <td style="vertical-align: top;"><span style="font-style: italic;">geode</span><br>
      </td>
      <td style="vertical-align: top;">Low power version AMD CPU. MMX,
SSE, SSE2, 3dNOW!, enhanced 3dNOW! Support<br>
      </td>
    </tr>
    <tr>
      <td style="vertical-align: top;"><em>winchip-c6</em></td>
      <td style="vertical-align: top;">IDT Winchip C6 CPU, dealt in
same way as i486 with additional MMX instruction
set support. </td>
    </tr>
    <tr>
      <td style="vertical-align: top;"><em>winchip2</em></td>
      <td style="vertical-align: top;">IDT Winchip2 CPU, dealt in same
way as i486 with additional MMX and 3dNOW! instruction set support. </td>
    </tr>
    <tr>
      <td style="vertical-align: top;">c3<br>
      </td>
      <td style="vertical-align: top;">Via C3 CPU with MMX and 3dNOW!
instruction set support. (No scheduling is
implemented for this chip.) </td>
    </tr>
    <tr>
      <td style="vertical-align: top;">c3-2<br>
      </td>
      <td style="vertical-align: top;">Via C3-2 CPU with MMX and SSE
instruction set support. (No scheduling is
implemented for this chip.)</td>
    </tr>
  </tbody>
</table>
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